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10162015 - Revision 11
- Modified ethernet clock multiplexer implementation to close timing with ethernet phy.
  New multiplexer removes support of 10BASET.
- New LED definition removes multiple functions mapping to LEDs, adds
  PHY connection status and DHCP status LEDs
    LED1 = 50 MHz clock (on CVA9 board) heartbeat
    LED2 = ADC_CLKA clock (from HF2 board) heartbeat
    LED3 = PTT active
    LED4 = DOT active
    LED5 = DASH active
    LED6 = ADC Overflow
    LED7 = PHY Connected
    LED8 = DHCP Address Assigned
- Removed DAC ALC hardware limit to fix low power out problem. Hardware uses whatever
  value is sent from PowerSDR
- Direct CW initializes to 60% drive level (for optimum spurs vs. power), this will be
  overwritten if commanded from PowerSDR.